3.3. Clash Compiler Flags


Use the VHDL backend for code generation. This currently emits VHDL 1993 source which can be consumed by other tools.


Use the Verilog backend for code generation. This currently emits Verilog 2001 source which can be consumed by other tools.


Use the SystemVerilog backend for code generation. This currently emits SystemVerilog 2012 source which can be consumed by other tools.


Set the debugging mode for the compiler, exposing additional output. The available options are

  • DebugNone to show no debug messages

  • DebugSilent to test invariants and error if any are violated. This is implicitly enabled by any debug flag

  • DebugFinal to show expressions after they have been completely normalized

  • DebugCount to count how often each transformation is applied

  • DebugName to show the names of transformations as they are applied

  • DebugTry to show names of tried and applied transformations

  • DebugApplied to show sub-expressions after they are rewritten

  • DebugAll to show all sub-expressions when a rewrite is attempted

Default: DebugNone


This flag exists for backwards compatibility. It is now possible to set debugging flags individually with -fclash-debug-invariants, -fclash-debug-info and -fclash-debug-count-transformations.


Check invariants while debugging and print warnings / errors which may be useful, such as alterting when unexpected changes occur or when a transformation introduces free variables / shadowing.


Specify the information to show about individual transformations while debugging. From least to most information, these are

  • None to show no information

  • FinalTerm to show the final result of normalization

  • AppliedName to show the names of applied transformations

  • AppliedTerm to show the result of applied transformations

  • TryName to show the names of attempted transforamtions, as well as the result of any transformations which are applied

  • TryTerm to show the names and results of all transformations attempted whether they were applied or not

    Default: None


Count the transformations that are applied and print a summary at the end of the normalization phase.


Saves all applied rewrites into FILENAME, for later analysis with the clash-term tool. When no filename is given it defaults to history.dat.


List the transformations that are to be debugged. This is given as a comma-separated list of transformations, e.g.

clash -fclash-debug-transformations inlineNonRep,topLet,appProp

Default: []


Only print debug output from applied transformation N and onwards.

clash -fclash-debug-transformations-from=21570

Default: 0


Only print debug output for N applied transformations.

clash -fclash-debug-transformations-limit=12

Default: MAX_INT


Specify the directory that generated HDL is written into. For example

clash -fclash-hdldir build/hdl

will create a directory build/hdl

Default: Either vhdl, verilog, or systemverilog depending on the synthesis target.


Specify the HDL synthesis tool which will be used. Available options are Vivado, Quartus and Other, but some synonyms for these exist (Xilinx and ISE are synonyms for Vivado, Altera and Intel are synyonyms for Quartus).

Default: Other


Don’t reuse previously generated output from Clash, instead generating HDL from a clean state. While this leads to longer builds, it can be useful in development.


Previously this flag was called -fclash-nocache, however this is now deprecated.

Default: Cache generated HDL


Check that all include directories (containing primitives) exist when running Clash. If any directory does not exist, an error is thrown.

Default: Check directories


Remove HDL directories before writing to them (if cache can’t be used). By default, Clash will only write to non-empty directories if it can prove all files in it are generated by a previous run. This option applies to directories of the various top entities, i.e., the subdirectories made in the directory passed in with -fclash-hdldir.

Default: Clean before build


Disable warnings for primitives that are annotated with warnAlways. This means warnings from annotations like

{-# ANN f (warnAlways "This primitive is dangerous") #-}

will not be shown when compiling.

Default: Show warnings


Change the number of times a function can undergo specialization.

Default: 20


Change the number of times a function f can undergo inlining inside some other function g. This prevents the size of g growing dramatically.

Default: 20


Set the threshold for function size. Below this threshold functions are always inlined (if it is not recursive).

Default: 15


Set the threshold for constant size. Below this threshold constants are always inlined. A value of 0 inlines all constants.

Default: 0


Set the threshold for unfolding potentially non-terminating bindings in the evaluator. A value of 0 only unfolds terminating bindings.

Default: 20


Set the bit width for the Int/Word/Integer types. The only allowed values are 32 or 64.

Default: Machine word size (WORD_SIZE_IN_BITS)


Print additional information with compiler errors if it as available. If there is extra information and this flag is not enabled, a message will be printed suggesting this flag.

Default: False


Enable support for floating point numbers. If this is disabled, Clash will not attempt to convert Float and Double values for hardware.

Default: False


Prefix the names of generated HDl components with a string. For example a component foo would be called xcorp_foo if run with

clash -fclash-component-prefix "xcorp"

Default: “”


The new inlining strategy for Clash inlines all functions which are not marked with NOINLINE or a synthesize attribute. The old inlining strategy differed, attempting only to inline functions which were deemed “cheap”. The old inlining strategy may be quicker in practice for some circuits.

Default: False


Disable extended identifiers, as used in some HDLs like VHDL to allow more flexibility with names. Clash will only generate basic identifiers if this is used.

Default: Escaped identifiers are allowed


Clash will only generate lower case basic identifiers if this is used. This affects places where the various HDLs only allow basic identifiers to be used, most notably module and file names.

Default: Disabled


Aggressively run the normalizer, potentially gaining much better runtime performance at the expense of compile time.

Default: False


Set the value to use when an undefined value is inserted into generated HDL. This flag can be suffixed with either 0 or 1 to force use of that bit, or left without a suffix to use a HDL-specific default (e.g. x in Verilog).

Default: Disabled


Remove all undefined branches from case expressions, replacing them with another defined value in the expression. If only one branch is defined, the case expression is elided completely. If no branches are defined the entire expression is replaced with a call to errorX.

Implies: -fclash-aggressive-x-optimization-blackboxes

Default: False


Allow blackboxes to detect undefined values and change their behavior accordingly. For example, if register is used in combination with an undefined reset value, it will leave out the reset logic entirely. This flag is enabled when using -fclash-aggressive-x-optimization.

Default: False


Generate metadata for use with Edalize. This generates edam.py files in all top entities with the configuration for building that entity. Users still need to edit this file to specify the EDA tool to use, and if necessary the device to target (for Quartus, Vivado etc.)

Default: False


When using one of --vhdl, --verilog, or --systemverilog, this flag refers to synthesis target. For example, running Clash with clash My.Module -main-is top --vhdl would synthesize My.Module.top.